library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.processor_pkg.all;

entity alu_tsb is
end entity alu_tsb;

architecture arch of alu_tsb is

	signal alu_in_op1	:	word_t;
	signal alu_in_op2	:	word_t;
	signal alu_in_opcode	:	mnemonic_t;
	signal alu_in_flags	:	flags_t;
	signal alu_out_res	:	word_t;	
	signal alu_out_flags	:	out_flags_t;
	
begin
	

	input:process is
	begin
		alu_in_op1 <= std_logic_vector(to_unsigned(3,32));
		alu_in_op2 <= std_logic_vector(to_unsigned(7,32));
		alu_in_opcode <= SHL;
		alu_in_flags <= (others => '0');
		wait;
	end process input;
	
	alu_instance : entity work.alu
		port map(in_op1 => alu_in_op1,
					in_op2 => alu_in_op2,
					in_opcode => alu_in_opcode,
					in_flags => alu_in_flags,
					out_res => alu_out_res,
					out_flags => alu_out_flags);
					
end architecture arch;